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C/C++ Source or Header  |  2008-12-24  |  2.4 KB  |  68 lines
  1. /* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
  2.  *
  3.  * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
  4.  *        http://www.simtec.co.uk/products/SWLINUX/
  5.  *
  6.  * This program is free software; you can redistribute it and/or modify
  7.  * it under the terms of the GNU General Public License version 2 as
  8.  * published by the Free Software Foundation.
  9.  *
  10.  * S3C2440 AC97 Controller
  11. */
  12.  
  13. #ifndef __ASM_ARCH_REGS_AC97_H
  14. #define __ASM_ARCH_REGS_AC97_H __FILE__
  15.  
  16. #define S3C_AC97_GLBCTRL                (0x00)
  17.  
  18. #define S3C_AC97_GLBCTRL_CODECREADYIE            (1<<22)
  19. #define S3C_AC97_GLBCTRL_PCMOUTURIE            (1<<21)
  20. #define S3C_AC97_GLBCTRL_PCMINORIE            (1<<20)
  21. #define S3C_AC97_GLBCTRL_MICINORIE            (1<<19)
  22. #define S3C_AC97_GLBCTRL_PCMOUTTIE            (1<<18)
  23. #define S3C_AC97_GLBCTRL_PCMINTIE            (1<<17)
  24. #define S3C_AC97_GLBCTRL_MICINTIE            (1<<16)
  25. #define S3C_AC97_GLBCTRL_PCMOUTTM_OFF            (0<<12)
  26. #define S3C_AC97_GLBCTRL_PCMOUTTM_PIO            (1<<12)
  27. #define S3C_AC97_GLBCTRL_PCMOUTTM_DMA            (2<<12)
  28. #define S3C_AC97_GLBCTRL_PCMOUTTM_MASK            (3<<12)
  29. #define S3C_AC97_GLBCTRL_PCMINTM_OFF            (0<<10)
  30. #define S3C_AC97_GLBCTRL_PCMINTM_PIO            (1<<10)
  31. #define S3C_AC97_GLBCTRL_PCMINTM_DMA            (2<<10)
  32. #define S3C_AC97_GLBCTRL_PCMINTM_MASK            (3<<10)
  33. #define S3C_AC97_GLBCTRL_MICINTM_OFF            (0<<8)
  34. #define S3C_AC97_GLBCTRL_MICINTM_PIO            (1<<8)
  35. #define S3C_AC97_GLBCTRL_MICINTM_DMA            (2<<8)
  36. #define S3C_AC97_GLBCTRL_MICINTM_MASK            (3<<8)
  37. #define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE        (1<<3)
  38. #define S3C_AC97_GLBCTRL_ACLINKON            (1<<2)
  39. #define S3C_AC97_GLBCTRL_WARMRESET            (1<<1)
  40. #define S3C_AC97_GLBCTRL_COLDRESET            (1<<0)
  41.  
  42. #define S3C_AC97_GLBSTAT                (0x04)
  43.  
  44. #define S3C_AC97_GLBSTAT_CODECREADY            (1<<22)
  45. #define S3C_AC97_GLBSTAT_PCMOUTUR            (1<<21)
  46. #define S3C_AC97_GLBSTAT_PCMINORI            (1<<20)
  47. #define S3C_AC97_GLBSTAT_MICINORI            (1<<19)
  48. #define S3C_AC97_GLBSTAT_PCMOUTTI            (1<<18)
  49. #define S3C_AC97_GLBSTAT_PCMINTI            (1<<17)
  50. #define S3C_AC97_GLBSTAT_MICINTI            (1<<16)
  51. #define S3C_AC97_GLBSTAT_MAINSTATE_IDLE            (0<<0)
  52. #define S3C_AC97_GLBSTAT_MAINSTATE_INIT            (1<<0)
  53. #define S3C_AC97_GLBSTAT_MAINSTATE_READY        (2<<0)
  54. #define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE        (3<<0)
  55. #define S3C_AC97_GLBSTAT_MAINSTATE_LP            (4<<0)
  56. #define S3C_AC97_GLBSTAT_MAINSTATE_WARM            (5<<0)
  57.  
  58. #define S3C_AC97_CODEC_CMD                (0x08)
  59.  
  60. #define S3C_AC97_CODEC_CMD_READ                (1<<23)
  61.  
  62. #define S3C_AC97_STAT                    (0x0c)
  63. #define S3C_AC97_PCM_ADDR                (0x10)
  64. #define S3C_AC97_PCM_DATA                (0x18)
  65. #define S3C_AC97_MIC_DATA                (0x1C)
  66.  
  67. #endif /* __ASM_ARCH_REGS_AC97_H */
  68.